Tuesday 21 October 2014
Sunday 19 October 2014
DSP LESSON PLANNING 2014-15
DEPARTMENT
OF ELECTRONICS AND COMMUNICATOIN ENGINNERING
Academic
Year: 2014-2015 Semester: Odd
LESSON
PLANNING
Semester:- V I I
Section :- ‘ A ’
Subject Name:-
DSP Algorithms & Architecture
Subject Code:- 10EC751
Name of the Subject Teacher:-
Rajendra Kulkarni
Name of
Subject Expert (Reviewer):- Prof. Ravindra Eklarkar
For the Period :
From 01-08-2014 To
19-11-2014
INITIAL BRIEFING & LAYING DOWN OF
OBJECTIVES
BY STUDENTS FOR THEMSELVES :
1. Student’s objectives viz this subject.
a) To study & learn about
DSP Algorithm & Architecture.
b) To learn about TMS320C54XX Processor instructions &
programming .
c) To learn about Interfacing & Applications of DSP
Processor.
2. Actions by students, to achieve their objectives.
(as
decided by students)
a) Attend classes regularly on time.
b) Refer various standard books.
c) Submit assignments on time.
d) Must & should follow college rules & discipline.
e) Must refer some IEEE papers.
f)
Should make use of
internet facility in proper way.
3. What student expect from Subject Teacher & organization
to
achieve their objectives.
a) Teachers should be regular to class.
b) Some power point presentation must be given for better
understanding.
c) University old question papers must be solved.
d) Assignments must be given to get thorough in the subject .
e) Teachers should appreciate and support new ideas.
f) Out of 25 I. A. Marks, 5 marks should be given for assignments,
attendance and discipline.
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S.N.
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Topic/Experiment
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Planned
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Executed
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Remarks
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No. of Hours
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Date
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No. of Hours
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Date
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Part-A
Unit 1: Introduction to
DSP
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1
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Introduction
, A DSPS/M,
The
Sampling Process
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1
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2
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Discrete
Time Sequences DFT&FFT
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1
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3
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LTI
Systems
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1
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4
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Digital Filters
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1
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5
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Decimation
& Interpolation
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1
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Unit 2 : Architecture for Programmable DSP
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6
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Introduction
, Basic Architectural Features
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1
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7
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DSP
Computational building blocks
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2
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8
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Bus Architecture & Memory
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1
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9
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Data
addressing capabilities
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1
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10
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Address Generation Unit
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1
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11
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Programmability
& Program Execution
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1
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12
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Features for
External Interfacing
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1
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Unit 3: Programmable DSP
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13
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Introduction,
Commercial DSP Devices
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2
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14
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Data Addressing Modes of TMS320C54XX DSP
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2
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15
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Memory Space of TMS320C54XX Program Control
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2
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Unit 4 : TMS320C54XXINSTRUCTION &
PROGRAMMING
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16
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On Chip Peripherals
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2
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17
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Interrupts of TMS320C54XX
DSP
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2
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18
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Pipeline Operation of TMS320C54XX
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2
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Unit 5 : Implementation of
Basic DSP Algorithm
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19
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Introduction , the
notation
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2
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20
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FIR Filters ;IIR Filters
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2
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21
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Interpolation of
Decimation Filters
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2
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Unit 6 : Implementation of
FFT Algorithm
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22
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Introduction An FFT Algorithm
for DFT Computation
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2
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23
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Overflow & Scanning
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2
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24
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Bit Reversed Index
Generation & implementation on
the TMS320C54XX
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2
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Unit 7 : Interfacing
memory & parallel I/O Peripherals To DSP Devices
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25
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Introduction, Memory Space
Organization ,External bus Interfacing Signals
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2
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26
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Memory & Parallel I/O Interface Programmed I/O
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2
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27
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Interrupts & I/O DMA
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2
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Unit 8 : Interfacing & Applications
of DSP Processor
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28
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Introduction, Synchronous
Serial Interface
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1
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29
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CODEC Interface circuit.
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1
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30
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DSP based Biotelemetry
Receiver
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1
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31
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A Speech Processing System
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1
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32
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An Image Processing System
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1
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33
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I
I. A .T
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1 .25
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34
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I I
I. A .T
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1 .25
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35
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I I I
I. A .T
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1 .25
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ASSIGNMENT
PART-A
Unit 1: Introduction
to DSP
1) Explain
the Decimation & Interpolation
Process, with an example.
2) The
sequence x(n) = [ 0 , 3 , 6 , 9
] is interpolated using interpolation sequence bk = [ 1/3 , 2/3 , 1 , 2/3 , 1/3 ] & the
interpolation factor of 3 . Find the interpolated sequence y(m).
3) Explain
with the help of B.D. DSP system &
timing diagram.
4) Explain
the Decimation & Interpolation Process. Find FIR interpolation for x(n) = [
0 , 3 , 6 , 9 ,12 ] interpolated using L
= 3 & Let w(m) =[
0,0,0,3,0,0,6,0,0,9,0,0,12 ] & bk
= [1/3 , 2/3 , 1 , 2/3 , 1/3].
5) In
brief explain the different DSP computational building blocks & give brief
explanation .
6) Write
a note on DFT & FFT .
7) Complete
DFT , FFT, DFT / FFT for N = 2,4,8,16,……..64K.
8) Write a note on LTI system.
Unit 2 : Architecture for Programmable DSP
1) Describe
the basic features that should be provided in the DSP architecture to be used
to implement the N th order
FIR filter ,
N-1
Y(n) = ∑ h(i) x(n-i)
; n = 0,1,2,3,……..
i=0
Where x(n) denotes the i/p sample , y(n) denotes the o/p sample
& h(i) denotes ith filter coefficient.
2) Design
a Digital filter for Nth order difference equation .
3) Giving
the structure explain 4X4 Braun
Multiplier.
4) Explain
Baugh-Wooley Multiplier for signed nos. Show the multiplication operation for
4X4 signed multiplication.
5) It
is required to find the sum of 64 nos. each represented by 16-bits.How many
bits should the accumulator have so that the sum can be computed without the
occurrence of overflow error or loss of accuracy?
6) If
in the above problem it is decided to have an accumulator with only 16 bits but
shift the nos. before the addition to prevent overflow ,by how many bits should
each no. be shifted?
7) If
all the nos. in the above problem are fixed point integers, what is the actual
sum of the nos.?
8) What is the error in the computation of the
sum in the above example?
9) Write
a note on Barrel shifter.
10) Design
a MAC unit & explain the function in brief.
11) If
the sum of 256 products is to be computed using a pipelined MAC unit, and if
the MAC execution time of the unit is 100 nsec ,what will be the total time
required to complete the operation?
12) Consider
a MAC units whose i/ps are 16-bit nos.
If 256 products are to be summed up in this MAC how many guard bits should be
provided for the accumulator to prevent overflow condition from occurring?
13) Draw
the schematic diagram of the saturation logic and explain the same.
14) With
a neat block diagram , explain ALU of a DSP s/m.
15) Write
short note on
i)
Overflow & Underflow ii) Guard bits.
16) Give
the comparison b/w
i) Von Neumann Architecture ii) Harvard
architecture
17)What is the importance of on chip
memory ? Why it is preferred
in the DSP architecture?
18)Define
addressing mode? What are the different types of
addressing modes ? Explain in detail.
19)What are the memory addresses of the operands in each of the
following cases of indirect addressing modes? In each case what
will be the content of the addrreg after the memory access?
Assume that the initial contents of the addrreg & offsetreg are
0200h & 0010h,respectively.
a) ADD *addrreg-
b) ADD+ *addrreg
c) ADD offsetreg+ , *addrreg
d) ADD *addrreg, offsetreg-
20) Explain the circular & bit-reversed addressing mode with the
help of algorithm.
21)A DSP has a circular buffer with the start & the end addresses as
0200h &
020Fh,respectively.What would be the new values of the
address pointer of the buffer if, in the course of address
computation ,it gets updated to
a) 0212h , b) 01FCh?
22)Repeat the above problem if the start & the end addresses of the
Circular buffer are
0210h & 0201h respectively ?
23)Compute the sequence in which the i/p data should be ordered
for a 16 point DIT FFT.
24)Draw the neat B.D. to explain the working of ADU.
25)Briefly explain
i)Program control ,ii) Program Sequencer , iii)H/W architecture ,
iv)Parallelism ,v)Pipelining
26)Explain
i)Single MAC implementation of an 8-tap FIR Filter
ii)Pipelined eight MAC
implementation of an 8-tap FIR Filter
iii) Parallel two MAC implementation of an 8-tap FIR
Filter
Unit 3:
Programmable DSP
1)List
the Architectural features of 3 fixed point DSPs.
2)Explain
the functional Architecture of TMS320C54XX
Processor.
3)How
the ALU of TMS320C54XX Processor works?
4)Draw
the functional diagram of Barrel shifter of ALU of
TMS320C54XX Processor.
Describe briefly.
5)Draw
the functional diagram of Multiplier/Adder unit of
TMS320C54XX Processor.
Describe briefly.
6)Explain
all types of addressing modes with an example. Draw
the suitable B.D.
wherever suitable.
7)Assume
the contents of AR3 to be 0200h,what will be the
contents after each of
the following TMS320C54XX Processor
addressing modes is used? Assume the
contents of AR0 are
20h.
i)
*AR3 + 0
ii) *AR3 - 0
iii)
*AR3 +
iv)
*AR3-
v)
*AR3
vi)
*+AR3(40h)
vii)
*+AR3(-40h)
8)
Assume that the register AR3with contents 1020h is selected
as the pointer for the circular buffer. Let
Bk=40h to specify the circular buffer size as 41h.Determine the start & end
addresses for the buffer. What will be the contents of the register AR3 after
the execution of the instruction LD *AR3+0%
, A ; if
the contents of register AR0 are 0025h?
9)
Assume the contents of AR3 to be 0200h,what will be the
contents after each of
the following TMS320C54XX Processor
addressing modes is used? Assume the
contents of AR0 are
20h.
i)
*AR3 + 0 B
ii)
*AR3
- 0 B
10)What
is the configuration of on chip DARAM , on chip SARAM
& ROM if MP/MC' = 0,OVLY = 1 & DROM = 0 for TMS320C54XX.
11)Repeat
the above problem if MP/MC'
= 1,OVLY = 1 & DROM =1.
12)Write
a note on program control.
Unit 4 : TMS320C54XX Instructions & Programming
1) Explain
the following instructions of TMS320C54XX Processor.
i)
Load & Store instructions
ii)
Arithmetic instructions
iii)
Logical instructions
iv)
Program Control instructions
v)
Multiply instruction(MPY)
vi)
Multiply & Accumulate instruction(MAC)
vii)
Multiply & Subtract instruction(MAS)
viii)
Multiply & Accumulate & Delay
(MACD) instruction
2) Differentiate
b/w MAC & MACD instructions by way of
explaining them.
3) Write
a program to find the sum of series of signed nos. as
specified below.
41Fh
A = ∑ X ( i )
i = 410h
Assume AR1as pointer to x(i) & AR2 as
counter for the nos.
4) By
means of a figure , show the pipeline operation of the
following sequences of TMS320C54XX instructions. Assume
initial value of AR3 is 80h and the
values stored in memory
locations 80h,81h,82h as 1,2&3.
LD *AR3 + , A
ADD #1000H, A
STL A, *AR3+
5) Describe
the operation of the following instructions of
TMS320C54XX Processor.
i)
MPY *AR2 - , *AR4 + 0 B
ii)
MAC *AR5
+ , #1234h , A
iii)
STH A,1,*AR2
iv)
SBBX SXM
6) Explain
the following assembler directives of TMS320C54XX
Processor.
i)
. mmregs ; ii) .global ; iii).include’xx’ ; iv).data ; v) .end; vi).bss
7)
WALP of TMS320C54XX Processor to compute the sum of
three product terms given by the equation
;
y(n) = h0 x(n) + h1 x(n-1) + h2 x(n-2) with usual notations.
Find y(n) for signed 16 bit data samples
& 16 bit constants.
8)Describe the operation of the following instructions with
respect to TMS320C54XX Processor :
i)
MAS *AR3- , *AR4+ , B,A
ii)
MPY #01234 , A
9)Explain
the operation of Serial I/O ports & H/W Timer of
TMS320C54XX Processor
on chip peripherals.
10)Describe
Host port interface & explain its signals.
11)Write
a note on Clock generator.
12)With
neat sketch explain six stage pipeline operation
TMS320C54XX execution.
PART-B
Unit 5 : Implementation of Basic DSP Algorithm
1)What
do you mean by Q notation used in DSP Algorithm
implementation ?What
are the values represented by 16 bit no.
N = 4000 H in Q15,Q7
& Q9 notation ?
2)
Determine the values of each of the following 16bit no.
represented using
the Q-notation 4400h as a Q0 no. , 4400h as
a Q15 no. &
4400h as a Q7 no.
3)Represent
each of the following as 16-bit nos. in the desired Q-
Notation. 0.3125 as a Q15 no. - 0.3125 as a Q 15 no. & 3.125 as a
Q7 no.
4)Write a TMS320C54XX program that
illustrate the
implementation of an
interpolating FIR filter of length 15 &
interpolating factor
5.
5)What
is an interpolation filter?Explain the implementation of
digital interpolation
using FIR filter & polyphase sub filter.
6)WALP
for TMS320C54XX Processor to multiply two Q15 nos.to
produce Q15 no. result.
7)WALP
to multiply two Q-15 nos.
8)Analyze
the following program to answer the questions at the
end. Assume that all
specified data locations are on the same
page starting at a0
Q15 notation is assumed.
.data
a0
.word 6000h
b1 .word 2000h
xn .word 4000h
yn .word 0h
ynm1 .word 3000h
.text
ld #a0,dp
ld a0,t
mpy xn,a
ld b1,t
mac ynm1,a
sth a,1,yn
i)
Determine the decimal values represented by
yn.
ii)
Determine the equation for yn implemented
by the above program.
Unit 6 : Implementation of FFT Algorithm
1a) Derive the equation to implement a
butterfly structure in
DITFFT Algorithm.
b) How many add/subtract & multiply
operations are needed to
compute the butterfly structure?
c)
Determine the optimum scaling factor .
2a) What minimum size FFT must be used to
compute a DFT of 40
Samples?
b)How many stages are required for FFT computation ?
c)How many butterflies are there per stage?
d)How many butterflies are needed for
the entire computation?
3) Write a TMS320C54XX program that
illustrates the
implementation of 8 point DITFFT Algorithm.
4)Determine the following for a 128 point
FFT computation:
i) No. of stages
ii) No. of butterflies needed for the entire computation
iii)No. of butterflies that need no twiddle factor
iv)No. of butterflies that require real twiddle factors
v)No.of butterflies that require complex twiddle factors.
5)Explain how scaling prevents overflow
conditions in the
butterfly computation.
6)With the help of implementation
structure ,explain the FFT
Algorithm for the DIT-FFT computation
on TMS320C54XX
Processor. Use ¼ as scale factor for
all butterflies.
7)Write the subroutine for Bit reverse address generation .
Explain the same.
8)Briefly explain scaling & derive the
expression for scaling for
optimum scaling factor for DIT FFT
Butterfly Algorithm.
Unit 7 : Interfacing Memory & Parallel I/O ,
Peripheral I/O
1)Explain briefly memory space
organization in TMS320C54XX
memory.
2)Draw the timing diagram for memory interface for read-read-write
sequence of operation. Explain the purpose of each signal
involved.
3) Draw the timing diagram for I/O
interface for read -write-read
sequence of operation. Explain the purpose of each signal
involved.
4)Explain the ADC interface in programmed
I/O mode with the help of
B.D. & flowchart.
5)Explain how the interrupts are handled in TMS320C54XX
Processor, with the help of flow chart.
6)Describe DMA w.r.t. TMS320C54XX
Processor .
7)Explain the register subaddressing technique for configuring DMA
operation.
8)Design an interface to connect 64K X 16 flash memory to a
TMS320C54XX Processor. The processor address bus is 16 bits.
9)Design a data memory system with address range 000800h –
000FFFh for a TMS320C54XX Processor. Use 2K X 8 SRAM memory
Chips.
10)Interface 8K X 16 program ROM to the TMS320C54XX Processor in
the address range 7FE000h – 7FFFFFh .
11)Design a circuit to interface a 4K X 16 & a 2K X 16 memory chip
to
realize program memory space for the TMS320C54XX Processor in
the address range 0FFFFFh –
0F0000h & 05F800h – 05FFFFh ,
respectively.
12)Design a circuit to interface 64 K words of the program memory
space from 0FFFFFh – 0F0000h for the TMS320C54XX Processor
using 16 K X 16 memory chips.
Unit 8 : Interfacing &
Applications of DSP Processor
1)With a neat B.D. & timing diagram for both transmit & receive
explain the signals involved in synchronous serial interface.
2)Explain PCM 3002 CODEC ,with the help of a neat B.D.
3)How to interface CODEC Device to TMS320C54XX
Processor? Explain.
4)Explain DSP based Biotelemetry receiver s/m ,with the help of B.D.
5)Explain how PPM signal is decoded at the receiving end using DSP.
6)Write a pseudo algorithm for determining heart rate(HR),using DSP.
7)what is Autocorrelation ? Explain.
8)With the help of a B.D. ,explain the Image compression &
Reconstruction using JPEG Encoder & Decoder.
TEXT BOOK:
1. “ Digital Signal
Processing “ ; Implementations using DSP
Microprocessors with examples from
TMS320C54xx , Avatar Singh
& S.Srinivasan , Thomson Learning ,2004.
REFERENCE
BOOKS:
1. Digital Signal Processing
: A Practical Approach , Ifeachor
E.C.
,Jervis B.W. , Pearson – Education ,
PHI/2002
2. “ Digital Signal
Processor “ ,B.Venkataramani & M.Bhaskar ,
TMH, 2002
3. “ Architectures for
Digital Signal Processing “ , Peter Pirsch , John
Weily , 2007
INTERNAL ASSESMENT TEST PORTION
I
INTERNAL ASSESMENT TEST
UNIT
– I
UNIT
– II
II INTERNAL ASSESMENT TEST
UNIT
– III
UNIT
– IV
UNIT
– V
III INTERNAL ASSESMENT TEST
UNIT
– VI
UNIT
– VII
UNIT
– VIII
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